1. Field of the Invention
The present invention relates to electrical and electronic circuits and systems. More specifically, the present invention relates to systems and methods for current switching within digital to analog converters.
2. Description of the Related Art
Currently ‘oversampled’ delta-sigma (ΔΣ) modulator type analog-to-digital (ADC) converters are used for applications requiring accurate conversion of analog signals to digital signals at high speed. As is known in the art, a ΔΣ ADC (also known as a sigma-delta modulator ADC) typically includes an integrator in front of a quantizer. The quantizer provides a digital staircase approximation of the analog input signal. A delta sigma modulator with multibit feedback uses single bit feedback. In this case, the quantizer is typically a single comparator. Further, a ΔΣ ADC includes one or more feedback loops, which include multi-bit (or single bit) feedback DACs, to avoid the accumulation of quantization errors and to stabilize the ΔΣ ADC.
Delta-sigma modulators allow for the use of low-resolution components running at a higher sampling rate to provide a high resolution ADC converter at a lower sampling rate. Delta-sigma modulators allow for lower costs and higher accuracy than could otherwise be achieved without a delta-sigma modulator. Sigma-delta modulator (ADC) converters include a delta-sigma modulator and a digital filter, which processes the output thereof.
A highly precise current switch is needed for current switching of continuous-time analog to digital converters (ADCs) employed in delta-sigma modulators. A simple differential pair of transistors driven by a clocked latch has been used in the past to provide current switching for ADCs used in delta-sigma modulators. However, simple differential pair current switches may be sensitive to thermal history and produce an effect known as ‘intersymbol interference’). That is, if the latch has been switched to one state for a sufficient period of time, one transistor heats more than the other and changes its switch threshold. When the signal driving the switch has a non-zero risetime, this has the effect of changing the timing of the switch transition. Such thermal errors are difficult to characterize and compensate for.
Traditional approaches for suppressing intersymbol interference include a return-to-zero (RZ) configuration where the DAC current is gated off during part of each clock cycle. However, this requires faster operation of the DAC switch, adds another data edge that is subject to clock jitter, and produces a much less smooth output.
More recently, Adams et al. described a scheme with two interleaved RZ DACs to provide a more continuous output than does a singe RZ DAC. (See “A 113dB SNR Oversampling DAC with Segmented Noise-Shaped Scrambling”, IEEE Solid-State Circuits Conference, 1998.) This approach consumes additional current, is subject to clock jitter, and does not cancel all thermal effects.
A Application entitled “Clocked D/A Converter,” also filed Jan. 21, 2004 as U.S. patent application Ser. No. 10/763,071, now U.S. Pat. No. 7,002,499, issued Feb. 21, 2006 by Todd Kaplan and Albert E. Cosand, the teachings of which are hereby incorporated herein by reference, describes a latch used as a DAC switch. Unfortunately, in its simplest form, this circuit is sensitive to the voltage swing at the output summing nodes. This sensitivity can be alleviated by the addition of a common-base output stage, but that may increase the required supply voltage.
Inasmuch as the ADC is typically used in continuous time feedback loop, the timing errors become errors in the analog signals output from the ADC.
Hence, a need remains in the art for a precise switch for use in applications such as a feedback digital to analog converter in a continuous time sigma-delta or delta-sigma modulator.